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PCI Express DIY hacking toolkit What This repository contains a set of tools and proof of concepts related to PCI-E bus. It includes HDL design which implements software controllable PCI-E gen 1.1 endpoint device for with Spartan-6 FPGA. In comparison with popular this design allows to operate with raw Transaction Level Packets (TLP) of PCI-E bus and perform full 64-bit memory read/write operations. It's early version of my first much or less complicated FPGA project, so the speed is quite slow (around 1-2 Mb/s), but in upcoming releases it will be significantly increased by connecting PCI-E endpoint to MicroBlaze soft processor with AXI DMA engine.
Think about it more as a 'theoretical' excercise. Years after the transition is complete, Apple will release the 'lock' of Intel only and I'm sure you will get to build your own beige box some day (Apple and Intel working together will get BTX pushed mighty faster) -- it will just take time. The complete lock to just 'Intel' right now is for the community to grow and get supported. Mac os x 104 tiger for intel x86iso torrent software. Intel has a complete platform strategy that current AMD (AMD, please create chipsets, this IS holding you back) cannot match. What I really want to know is what kind of motherboard, and given an apple northbridge (say from another old apple machine, is it even just a chip like htat??) could we build something, possibly with a little soldering.
However, even such low speed is more than enough for reliable implementation of various practical attacks over PCI-E bus: to demonstrate applied use cases of the design, for pre-boot DMA attacks on UEFI based machines which allow executing arbitrary UEFI DXE drivers during platform init. Shows how to use pre-boot DMA attacks to inject into the enabled Windows 10 Enterprise running on UEFI Secure Boot enabled platform. Provided Hyper-V backdoor PoC might be useful for reverse engineering and exploit development purposes, it for inspecting of hypervisor state (VMCS, physical/virtual memory, registers, etc.) from guest partition and perform the guest to host VM escape attacks. Contents • s6_pcie_microblaze.xise − Xilinx ISE project file. • microblaze/pcores/axis_pcie_v1_00_a − Custom peripheral module which allows connecting PCI Express integrated endpoint block of Spartan-6 FPGA as raw TLP stream to MicroBlaze soft processor core.
It shall be protected by at least three physical security features from the list contained in Appendix A to Part 2 of Doc 9303. Doc 4444 icao na russkom. The SID shall be protected from tampering, photograph substitution or other fraudulent activity by adherence to the requirements of Part 2 of Doc 9303, “Specifications for the Security of the Design, Manufacture and Issuance of MRTDs”.
• sdk/srec_bootloader_0 − Simple bootloader for MicroBlaze soft processor, it using SREC image format and onboard linear flash memory of SP605 to load and store main MicroBlaze program. • sdk/main_0 − Main program for MicroBlaze soft processor, it forwards raw TLP packets of PCI-E bus into the TCP connection using onboard Ethernet port of SP605. • python/pcie_lib.py − Python library that talks over the network to main MicroBlaze program running on SP605 board. • python/pcie_mem.py − Command line program that dumps host RAM into the screen or output file by sending MRd TLPs. • python/pcie_mem_scan.py − Command line program that scans target host for physical memory ranges accessible over PCI-E bus, it's useful for a security audit of IOMMU enabled platforms (examples:,,, ). • python/uefi_backdoor_simple.py − Command line program for pre-boot DMA attack which injects dummy UEFI driver into the target. • python/uefi_backdoor_hv.py − Command line program for pre-boot DMA attack which injects Hyper-V VM exit handler backdoor into the target.